Various Instructions for five stage Pipeline
Let us consider following decomposition of instruction execution into five stages. These are give as follows below.
- Fetch Instruction (IF) :
It reads the next expected instruction into the buffer.IR β Mem [PC] ; PC β PC + 4 ;
- Instruction Decoding (ID) :
In this, there are following steps:- Instruction Decoding, in which determines opcode and operand specifiers.
- Calculate Operand, in which calculates effective address of each source operand.
- Fetch Operands, in which fetch each operand from memory.
A β Regs [IR6, 10] ; B β Regs [IR11, ..., 15] ; Immediate β (IR16)16## (IR16, ..., 31)
- Execute Instruction (EX) :
It performs indicated operation.Memory ref: ALUoutput β A + Immediate ; Reg-Reg ALU: ALU β A func B ; Reg-Imm ALU: ALUoutput β A op Immediate ; Branch: ALUoutput β PC + Immediate; Cond * (A op 0)
- Memory access/branch completion cycle (MEM) :
It accesses memory.Memory ref: LMD β Mem [ALUoutput] or Mem (ALUoutput) β B Branch: if (cond) PC β ALUoutput
- Write Operand (WO) :
It stores the result.Reg-Reg ALU: Regs [R16, ...., 20] β ALUoutput ; Reg-Imm ALU: Regs [R11, ..., 15] β ALUoutput ; Reg-Reg ALU: Regs [R11, ...., 15] β LMD ;