Implementation of Different Gates with 2:1 Mux

Given below are the Implementation of Different gate using 2:1 Mux

Implementation of NOT gate using 2 : 1 Mux

The Not gate from 2:1 Mux can be obtained by

• Connect the input signal to one of the data input lines(I0).
• Then connect a line (0 or 1) to the other data input line(I1)
• Connect the same input line Select line S0 which is connected to D0.

Given Below is the Diagram for the Logical Representation of NOT gate using 2 : 1 Mux

Implementation of AND gate using 2 : 1 Mux

The And gate from 2:1 Mux can be obtained by

• Connect the input Y to I1.
• Connect the input X to the selection line S0.
• Connect a line(0) to I0.

Given Below is the Diagram for the Logical Representation of AND gate using 2 : 1 Mux
 

For further more on the Implementation of AND gate using 2 : 1 Mux
 

Implementation of OR gate using 2 : 1 Mux

The OR gate from 2:1 Mux can be obtained by  

• Connect input X to the selection line S0.
• Connect input Y to I1.
• Connect Line(1) to I1.

Given Below is the Diagram for the Logical Representation of OR gate using 2 : 1 Mux

Implementation of NAND, NOR, XOR and XNOR gates requires two 2:1 Mux. First multiplexer will act as NOT gate which will provide complemented input to the second multiplexer. 
 

Implementation of NAND gate using 2 : 1 Mux

The NAND gate from 2:1 Mux can be obtained by  

• In first mux take inputs and 1 and 0 and y as selection line.
• In Second MUX the Output from mux is connected to I1.
• line(1) is given to the I0.
• x is given as selection line for the second Mux.

Given Below is the Diagram for the Logical Representation of NAND gate using 2 : 1 Mux
 

For further more on the Implementation of NAND gate using 2 : 1 Mux

 

Implementation of NOR gate using 2 : 1 Mux

The Nor gate from 2:1 Mux can be obtained by  

• In first mux take inputs and 1 and 0 and y as selection line.
• In Second MUX the Output from mux is connected to I0.
• line(0) is given to the I1.
• x is given as selection line for the second Mux.

Given Below is the Diagram for the Logical Representation of NOR gate using 2 : 1 Mux
 

For further more on the Implementation of NOR gate using 2 : 1 Mux

Implementation of EX-OR gate using 2 : 1 Mux

The Nor gate from 2:1 Mux can be obtained by  

• In first mux take inputs and 1 and 0 and y as selection line.
• In Second MUX the Output from mux is connected to I1.
• y is given to the I0.
• x is given as selection line for the second Mux.

Given Below is the Diagram for the Logical Representation of EX-OR gate using 2 : 1 Mux
 

Implementation of EX-NOR gate using 2 : 1 Mux

Given Below is the Diagram for the Logical Representation of EX-OR gate using 2 : 1 Mux

The Nor gate from 2:1 Mux can be obtained by  

• In first mux take inputs and 1 and 0 and y as selection line.
• In Second MUX the Output from mux is connected to I0.
• y is given to the I1.
• x is given as selection line for the second Mux.

In this article we will go through the multiplexer, we will first define what is a multiplexer then we will go through its types which are 2×1 and 4×1, then we will go through the Implementation of the 2×1 mux and higher mux with lower order mux, At last we will conclude our article with some applications, advantages and some FAQs.